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| Integrated Circuit Systems, Inc. ICS9248-50 Frequency Timing Generator for Pentium II Systems General Description The ICS9248-50 is the Main clock solution for Notebook designs using the Intel 440BX style chipset. Along with an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system. Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-50 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Features * Generates the following system clocks: - 2 CPU (2.5V) up to 100MHz. - 6 PCI (3.3V) @ 33.3MHz (Includes one free running). - 2 REF clks (3.3V) at 14.318MHz. Skew characteristics: - CPU - CPU<175ps - PCI - PCI < 500ps - CPU(early) - PCI = 1.5ns - 4ns. Supports Spread Spectrum modulation for CPU and PCI clocks, 0.5% down spread Efficient Power management scheme through stop clocks and power down modes. Uses external 14.318MHz crystal, no external load cap required for CL=18pF crystal. 28-pin (209 mil) SSOP package * * * Block Diagram * * Pin Configuration 28-Pin SSOP Power Groups VDD, GND = PLL core VDDREF, GNDREF = REF(0:1), X1, X2 VDDPCI, GNDPCI = PCICLK_F, PCICLK (0:4) VDD48, GND48 = 48MHz, 48/24MHz 0278I--06/03/03 ICS9248-50 Pin Descriptions Pin number 1 2 3 4 5,6,9,10,11 7 8 12 13 14 15 16 Pin name GNDREF X1 X2 PCICLK_F PCICLK (1:5) GNDPCI VDDPCI VDD48 48 MHz TS#/48/24MHz GND48 SEL 100/66# Type Power Input Output Output Output Power Power Power Output Output Power Input Description Ground for 14.318 MHz reference clock outputs 14.318 MHz crystal input 14.318 MHz crystal output 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP# 3.3 V PCI clock outputs, generating timing requirements for Pentium IIa Ground for PCI clock outputs 3.3 V power for the PCI clock outputs 3.3 V power for 48/24 MHz clocks 3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices 3.3 V 48 or 24 MHz output and Tri-state option, active low = tri state mode for testing, active high = normal operation Ground for 48/24 MHz clocks control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100 MHz frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Asynchronous active low input pin used to stop the CPUCLK in active low state, all other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at least 3 CPU clocks. Isolated 3.3 V power for core Synchronous active low input used to stop the PCICLK in active low state. It will not effect PCICLK_F or any other outputs. Isolated ground for core Ground for CPU clock outputs 2.5 V CPU clock outputs 2.5 V power for CPU clock outputs 3.3 V 14.318 MHz reference clock output and power-on spread spectrum enable option. Active low = spread spectrum clocking enable. Active high = spread spectrum clocking disable. 3.3 V 14.318 MHz reference clock output and power-on 48/24 MHz select option. Active low = 48 MHz output at pin 14. Active high = 24 MHz output at pin 14. 3.3 V power for 14.318 MHz reference clock outputs. 17 PD# Input 18 19 20 21 22 23,24 25 26 CPU_STOP# VDD PCI-Stop# GND GNDL CPUCLK(1:0) VDDL REF1/SPREAD# Input Power Input Power Power Output Power Output 27 28 REF0/SEL48# VDDREF Output Power 0278I--06/03/03 2 ICS9248-50 Select Functions (Functionality determined by TS# and SEL100/66# pin, see below) Functionality Tristate Testmode CPUCLK HI - Z TCLK/2 1 PCI, PCI_F HI - Z TCLK/6 1 REF0 HI - Z TCLK1 Notes: 1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode. SEL 100/66# 0 0 0 0 1 1 1 1 TS# 0 1 0 1 Function Tri-State (Reser ved) (Reser ved) Active 66.6MHz CPU, 33.3 PCI Test Mode (Reser ved) (Reser ved) Active 100MHz CPU, 33.3 PCI Power Management Clock Enable Configuration C P U _ S TO P # X 0 0 1 1 P C I _ S TO P # X 0 1 0 1 P W R _ DW N # 0 1 1 1 1 CPUCLK L ow Low Low 100/66.6MHz 100/66.6MHz PCICLK L ow Low 33.3 MHz Low 33.3 MHz PCICLK_F L ow 33.3MHz 33.3MHz 33.3MHz 33.3MHz REF Stopped Running Running Running Running Cr ystal Off Running Running Running Running VCOs Off Running Running Running Running Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also. ICS9248-50 Power Management Requirements SIGNAL CPU_ STOP# PCI_STOP# PD# SIGNAL STATE 0 (Disabled)2 1 (Enabled)1 0 ( D i s a bl e d ) 2 1 (Enabled)1 1 ( N o r m a l O p e ra t i o n ) 3 0 (Power Down)4 L a t e n cy No. of rising edg es of free running PCICLK 1 1 1 1 3ms 2max Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF will be stopped independant of these. 0278I--06/03/03 3 ICS9248-50 CPU_STOP# Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-50. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs. Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-50. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state. PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9248-50. It is used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-50 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state. 0278I--06/03/03 4 ICS9248-50 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internally by the ICS9248-50 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are don't care signals during the power down operations. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated. 0278I--06/03/03 5 ICS9248-50 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . 0C to +115C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, V DDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Clk Stabilization Skew1 1 SYMBOL VIH VIL IIH I IL1 I IL2 I DD3.3OP66 IDD3.3OP100 I DD2.5OP66 IDD2.5OP100 IDD3.3PD Fi CIN CINX Ttrans TSTAB TCPU-PCI CONDITIONS MIN 2 VSS - 0.3 -5 -200 TYP VIN = V DD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From V DD = 3.3 V to 1% target Freq. VT = 1.5 V; VTL = 1.25 V 0.1 2.0 -100 60 66 16 23 70 MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 180 mA 180 mA 72 mA 100 mA 600 16 5 45 3 3 mA MHz pF pF ms ms ns 11 27 14.318 36 1.5 3 4 0278I--06/03/03 6 ICS9248-50 Electrical Characteristics - CPUCLK TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter Jitter Jitter, Absolute 1 SYMBOL V OH2B V OL2B IOH2B IOL2B t r2B1 t f2B1 dt2B1 tsk2B1 CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, V OL = 0.4 V VT = 1.25 V MIN 1.8 TYP 2.3 0.31 27 0.4 0.4 44 10 -250 1.15 1.4 48 134 10 186 150 MAX UNITS V 0.4 V -27 mA mA 1.6 1.6 55 175 10.5 200 +250 ns ns % ps ns ps ps VT = 1.25 V period(norm) VT = 1.25 V; 100MHz t jcyc-cyc2B1 t jabs2B1 VT = 1.25 V VT = 1.25 V Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF/48MHz/24MHz TA = 0 - 70C; V DD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Jitter1 Jitter1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5 tj1s5 tjabs5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = VT = VT = VT = VT = 1.5 V 1.5 V, 1.5 V, 1.5 V, 1.5 V, MIN 2.6 16 TYP 3.1 0.17 -44 42 1.4 1.1 MAX UNITS V 0.4 V -22 mA mA 4 4 55 250 800 250 800 ns ns % ps ps ps ps 45 REF REF 48 MHz 48 MHz 53 185 385 169 469 0278I--06/03/03 7 ICS9248-50 Electrical Characteristics - PCICLK TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time Skew 1 1 1 SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 t sk1 tjcyc-cyc tj1s tjabs CONDITIONS IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = VT = VT = VT = 1.5 V 1.5 V 1.5 V 1.5 V MIN 2.1 TYP 3.3 0.1 16 1.6 1.8 45 50 222 186 52 200 MAX UNITS V 0.4 V -22 mA 57 mA 2 2 55 500 500 150 500 ns ns % ps ps ps ps Duty Cycle Jitter1 1 Guaranteed by design, not 100% tested in production. 0278I--06/03/03 8 ICS9248-50 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended. Capacitor Values: C1, C2 : Crystal load values determined by user All unmarked capacitors are 0.01F ceramic 0278I--06/03/03 9 ICS9248-50 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 1.65 0.22 2.00 1.85 0.38 .002 .065 .009 .079 .073 .015 A A1 A2 b c D E E1 e L N VARIATIONS N 8 14 16 18 20 22 24 28 30 38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0 8 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0 8 D mm. MIN 2.70 5.90 5.90 6.90 6.90 7.90 7.90 9.90 9.90 12.30 MAX 3.30 6.50 6.50 7.50 7.50 8.50 8.50 10.50 10.50 12.90 MIN .106 .232 .232 .271 .271 .311 .311 .390 .390 .484 D (inch) MAX .130 .256 .256 .295 .295 .335 .335 .413 .413 .508 6/1/00 Rev B MO-150 JEDEC Doc.# 10-0033 Ordering Information ICS9248yF-50-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0278I--06/03/03 10 |
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